1. Field of the Invention
The present invention relates to the field of manufacturing of integrated circuits.
2. Discussion of the Related Art
More specifically, in the field of integrated circuits, primary components have to be separated and more or less laterally isolated from one another. The most current technology to reach such results is the so-called LOCOS technology in which the various primary components are separated from one another by thick oxide layers formed by thermal growth. Another developing technique is the so-called well isolation technology, called xe2x80x9cBOXxe2x80x9d technology. In BOX technology, the intervals between primary components are formed of trenches grooved by anisotropic etching into the upper surface of a single crystal silicon wafer and filled with an insulator, usually silicon oxide, the upper surface being planarized by several techniques, for example by chem-mech polishing (CMP) with a stop on a silicon nitride layer previously formed above the silicon area to be isolated.
The present invention relates to integrated circuits using this latter technique of isolation between primary components.
It more specifically aims at implementing bipolar transistors of optimum performance, notably as concerns the reduction of stray capacitances and thus the operating speed of these transistors.
Another object of the present invention is to obtain bipolar transistors with reduced access resistances.
Another object of the present invention is to obtain the smallest possible bipolar transistors.
Another object of the present invention is to implement such bipolar transistors by techniques commonly used in the field of manufacturing of integrated circuits.
To achieve these and other objects, the present invention provides a bipolar transistor laterally isolated by a well, wherein a first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor base and a second portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor emitter.
According to an embodiment of the present invention, a layer of an SiGe-type material is formed at the interface between the island and the polysilicon having the same conductivity type as the transistor emitter.
The present invention also provides a method for manufacturing a bipolar transistor including the steps of forming an island of an epitaxied layer of the first conductivity type surrounded with a well filled with insulator, etching a portion at least of the upper internal periphery of the well by an anisotropic etching method selective with respect to the epitaxied layer to form a hollowed portion, filling the hollowed portion with polysilicon of the second conductivity type, bringing the upper surface of the polysilicon to be at the same level as the upper surface of the island, performing a base implantation of the second conductivity type, and depositing a second layer of polysilicon of the first conductivity type on a portion of the island and in a shifted manner with respect to the hollowed portion.
According to an embodiment of the present invention, the bipolar transistor manufacturing method includes the steps of forming an island of an epitaxied layer of the first conductivity type-surrounded with a well filled with insulator, etching a first portion of the upper internal periphery of the well to form a first hollowed portion, filling the first hollowed portion with polysilicon of the second conductivity type, performing a base implant of the second conductivity type, etching a second portion of the upper internal periphery of the oxide well to form a second hollowed portion, and filling the second hollowed portion with polysilicon of the first conductivity type.
According to an embodiment of the present invention, the method includes the step of siliciding the apparent surfaces of the polysilicon regions.
The foregoing objects, characteristics and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.